The present invention relates to a semiconductor device and is preferably applicable to, for example, a semiconductor device incorporating a power on reset circuit.
Patent Document 1 discloses a reset circuit including a voltage fluctuation detection circuit and a voltage monitoring timer circuit. When supply voltage is turned on, the voltage fluctuation detection circuit outputs a voltage fluctuation signal in response to the arrival of the supply voltage at a threshold voltage. The voltage monitoring timer circuit is reset by a voltage fluctuation signal and expires when a certain time has passed. The reset circuit resets a microcomputer during a standby period from when the voltage monitoring timer circuit is reset to when it expires.
Patent Document 2 discloses a voltage detection circuit, a reset circuit, and a delay circuit including a counter circuit. When supply voltage takes a normal value, the voltage detection circuit outputs a voltage detection signal; after it carries out a predetermined counting operation through the counter circuit, it outputs a count up signal. The reset circuit outputs a reset canceling signal in response to the output of the count up signal.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2007-249777
[Patent Document 2] Japanese Unexamined Patent Publication No. Hei 06(1994)-096238